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september 2011 doc id 16107 rev 8 1/28 28 TDA7498 100-watt + 100-watt dual btl class-d audio amplifier features 100-w + 100-w output power at thd = 10% with r l = 6 and v cc = 36 v 80-w + 80-w output power at thd = 10% with r l = 8 and v cc = 34 v wide-range single-supply operation (14 - 39 v) high efficiency ( = 90%) four selectable, fixed gain settings of nominally 25.6 db, 31.6 db, 35.1 db and 37.6 db differential inputs minimize common-mode noise standby and mute features short-circuit protection thermal overload protection externally synchronizable description the TDA7498 is a dual btl class-d audio amplifier with single power supply designed for home systems and active speaker applications. it comes in a 36-pin powersso package with exposed pad up (epu) to facilitate mounting a separate heatsink. powersso36 with exposed pad up table 1. device summary order code operating temp. range package packaging TDA7498 -40 to 85 c powersso36 (epu) tube TDA7498tr -40 to 85 c powersso36 (epu) tape and reel www.st.com
contents TDA7498 2/28 doc id 16107 rev 8 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 for r l = 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2.2 for r l = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.1 master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.2 slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TDA7498 list of figures doc id 16107 rev 8 3/28 list of figures figure 1. internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connections (top view, pcb view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. test circuit for characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. output power (thd = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. thd vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. thd vs. frequency (1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. thd vs. frequency (100 mw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. fft performance (0 dbfs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. fft performance (-60 dbfs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. output power (thd = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. thd vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. thd vs. frequency (1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. thd vs. frequency (100 mw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. fft performance (0 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 18. fft performance (-60 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 19. applications circuit for 6- or 8- speakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 20. standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21. turn on/off sequence for minimizing speaker ?pop? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 22. input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24. typical lc filter for a 8- speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 25. typical lc filter for a 6- speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. behavior of pin diag for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 27. powersso36 epu outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of tables TDA7498 4/28 doc id 16107 rev 8 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 7. mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. how to set up synclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. powersso36 epu dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TDA7498 device block diagram doc id 16107 rev 8 5/28 device block diagram figure 1 shows the block diagram of one of the two identical channels of the TDA7498. figure 1. internal block diagram (showing one channel only)
pin description TDA7498 6/28 doc id 16107 rev 8 1 pin description 1.1 pinout figure 2. pin connections (top view, pcb view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 32 33 34 35 36 19 20 21 22 23 24 25 26 27 vss sub_gnd outpb outpb pgndb pgndb pvccb pvccb outnb outnb outna outna pvcca pvcca pgnda pgnda outpa outpa pgnd vddpw stby mute inpa inna rosc synclk vdds sgnd diag svr gain0 gain1 inpb innb vref svcc ep, exposed pad connect to ground
TDA7498 pin description doc id 16107 rev 8 7/28 1.2 pin list table 2. pin description list number name type description 1 sub_gnd pwr connect to the frame 2,3 outpb o positive pwm for right channel 4,5 pgndb pwr power stage ground for right channel 6,7 pvccb pwr power supply for right channel 8,9 outnb o negative pwm output for right channel 10,11 outna o negative pwm output for left channel 12,13 pvcca pwr power supply for left channel 14,15 pgnda pwr power stage ground for left channel 16,17 outpa o positive pwm output for left channel 18 pgnd pwr power stage ground 19 vddpw o 3.3-v (nominal) regulator output referred to ground for power stage 20 stby i standby mode control 21 mute i mute mode control 22 inpa i positive differential input of left channel 23 inna i negative differentia l input of left channel 24 rosc o master oscillator frequency-setting pin 25 synclk i/o clock in/out for external oscillator 26 vdds o 3.3-v (nominal) regulator output referred to ground for signal blocks 27 sgnd pwr signal ground 28 diag o open-drain diagnostic output 29 svr o supply voltage rejection 30 gain0 i gain setting input 1 31 gain1 i gain setting input 2 32 inpb i positive differential input of right channel 33 innb i negative differentia l input of right channel 34 vref o half vdds (nominal) referred to ground 35 svcc pwr signal power supply 36 vss o 3.3-v (nominal) regulator output referred to power supply - ep - exposed pad for heatsink, to be connected to ground
electrical specifications TDA7498 8/28 doc id 16107 rev 8 2 electrical specifications 2.1 absolute maximum ratings 2.2 thermal data 2.3 recommended operating conditions 2.4 electrical specifications unless otherwise stated, the values in the table below are specified for the conditions: v cc =36v, r l = 6 , r osc = r3 = 39 k , c8 = 100 nf, f = 1 khz, g v = 25.6 db ta m b = 2 5 c. table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage for pins pvcca, pvccb, svcc 44 v v i voltage limits for input pins stby, mute, inna, inpa, innb, inpb, gain0, gain1 -0.3 to 3.6 v t j operating junction temperature -40 to 150 c t stg storage temperature -40 to 150 c table 4. thermal data symbol parameter min typ max unit r th j-case thermal resistance, junction to case - 2 3 c/w table 5. recommended operating conditions symbol parameter min typ max unit v cc supply voltage for pins pvcca, pvccb, svcc 14 - 39 v tamb ambient operating temperature -40 - 85 c table 6. electrical specifications symbol parameter condition min typ max unit i q total quiescent current no lc filter, no load - 40 60 ma i qstby quiescent current in standby - - 1 10 a v os output offset voltage play mode -100 - 100 mv mute mode -60 - 60 i ocp overcurrent protection threshold r l = 0 67- a
TDA7498 electrical specifications doc id 16107 rev 8 9/28 t j junction temperature at thermal shutdown - - 150 - c r i input resistance differential input 48 60 - k v ovp overvoltage protection threshold - 42 43 - v v uvp undervoltage protection threshold - --8v r dson power transistor on resistance high side - 0.2 - low side - 0.2 - p o output power thd = 10% - 100 - w thd = 1% - 78 - p o output power r l = 8 , thd = 10% - 80 - w p d dissipated power p o = 100 w + 100 w, thd = 10% -20-w efficiency p o = 100 w + 100 w - 90 - % thd total harmonic distortion p o = 1 w - 0.1 - % g v closed-loop gain gain0 = l, gain1 = l 24.6 25.6 26.6 db gain0 = l, gain1 = h 30.6 31.6 32.6 gain0 = h, gain1 = l 34.1 35.1 36.1 gain0 = h, gain1 = h 36.6 37.6 38.6 g v gain matching - -1 - 1 db c t crosstalk f = 1 khz, p o = 1 w 5070- db en total input noise a curve, g v = 20 db - 15 - v f = 22 hz to 22 khz - 25 50 svrr supply voltage rejection ratio fr = 100 hz, vr = 0.5 vpp, c svr = 10 f -70-db t r , t f rise and fall times - - 50 - ns f sw switching frequency internal oscillator 290 310 330 khz f swr output switching frequency range with internal oscillator (1) 250 - 400 khz with external oscillator (2) 250 - 400 v inh digital input high (h) - 2.3 - - v v inl digital input low (l) - - 0.8 table 6. electrical specifications (continued) symbol parameter condition min typ max unit
electrical specifications TDA7498 10/28 doc id 16107 rev 8 v stby pin stby voltage high (h) - 2.7 - - v pin stby voltage low (l) - - 0.5 v mute pin mute voltage high (h) - 2.5 - - v pin mute voltage low (l) - - 0.8 a mute mute attenuation v mute = l, v stby = h - 70 - db 1. f sw = 10 6 / ((16 * r osc + 182) * 4) khz, f synclk = 2 * f sw with r3 = 39 k (see figure 19. ). 2. f sw = f synclk / 2 with the external oscillator. table 6. electrical specifications (continued) symbol parameter condition min typ max unit
TDA7498 characterizations doc id 16107 rev 8 11/28 3 characterizations 3.1 test circuit figure 3 shows the test circuit with which the characterization curves, shown in the next sections, were measured. figure 4 shows the pcb layout. figure 3. test circuit for characterizations l+ r+ r- vcc gnd l+ l- r+ r- tda749 8 mute s tby 3 v 3 power s uppl y s ingle-ended * * * * * inp u t cla ss -d amplifier * * * * s ingle-ended inp u t lo a d = 6 ohm for for frequency s hift output input l- * lc filter component s lo a d l1,l2,l 3 ,l4 c20,c26 c1 8 ,c22,c24,c2 8 6 ohm 8 ohm 22 u h 22 u h 470 nf 6 8 0 nf 220 nf 220 nf c5 100nf r 3 3 9k l4 22 u h c1 1 u f c2 1 u f c11 1 u f c12 1 u f c 8 100nf c25 100nf c19 100nf c27 33 0pf r6 22r c40 220nf c41 220nf c21 33 0pf r5 22r c42 220nf c4 3 220nf c14 1nf 3 2 inpb 3 6 v ss 9 outnb 5 pgndb 7 pvccb 3 outpb 10 outna 12 pvcca 14 pgnda 16 outpa 33 innb 8 outnb 4 pgndb 21 mute 6 pvccb 2 outpb 29 s vr 11 outna 1 s ub_gnd 22 inpa 2 3 inna 27 s gnd 26 vdd s 2 8 diag 19 vddpw 1 8 pgnd 20 s tby 24 ro s c 3 1 gain1 3 5 s vcc 3 0 gain0 25 s ynclk 17 outpa 15 pgnda 3 4 vref 1 3 pvcca ic1 tda749 8 r1 100k r7 22r c6 100nf r4 120k r2 33 k r 8 6. 8 k c26 6 8 0nf c10 100nf c20 6 8 0nf j6 j5 2 1 3 s 1 2 1 3 s 2 c29 2.2 u f 2 gnd 1 out 3 in ic2 l49 3 1cz 3 3 1 2 j2 j 8 j7 + c2 3 2200 u f 50v l 3 22 u h l1 22 u h l2 22 u h j4 c 3 0 1 u f c 3 1 1 u f r14 100k r15 8 r c2 8 220nf r16 8 r c24 220nf r17 8 r c1 8 220nf r1 8 8 r c22 220nf 1 2 3 4 j 3 2 4 1 3 j1 r1 3 47k c1 3 1nf + c15 2.2 u f 16v + c7 2.2 u f 16v d1 1 8 v c9 100nf c4 1nf c 3 1nf c16 10 u f 10v c17 10 u f 10v r9 1 8 0k 1 2 3 q1 ktc 38 75( s ) diag vcc 3 v 3 3 v 3 f s f s vdd s vdd s
characterizations TDA7498 12/28 doc id 16107 rev 8 figure 4. test board
TDA7498 characterizations doc id 16107 rev 8 13/28 3.2 characterization curves unless otherwise stated the measurements were made under the following conditions: v cc = 36 v, f = 1 khz, g v = 25.6 db, r osc = 39 k , c osc = 100 nf, tamb = 25 c 3.2.1 for r l = 6 figure 5. output power (thd = 10%) vs. supply voltage figure 6. thd vs. output power 10 120 20 3 0 40 50 60 70 8 0 9 0 100 110 o u tp u t power (w) +10 + 3 6 +12 +14 +16 +1 8 +20 +22 +24 +26 +2 8 + 3 0+ 3 2+ 3 4 su pply volt a ge (v) 0.005 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 thd+n ( % ) 100m 200 200m 500m 1 2 5 10 20 50 100 o u tp u t power (w) f = 1 khz f = 100 hz
characterizations TDA7498 14/28 doc id 16107 rev 8 figure 7. thd vs. frequency (1 w) figure 8. thd vs. frequency (100 mw) figure 9. frequency response thd+n ( % ) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) 0.01 2 0.02 0.05 0.1 0.2 0.5 1 0.01 2 0.02 0.05 0.1 0.2 0.5 1 thd+n ( % ) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) - 3 + 3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 ampl (db) 10 20k 20 50 100 200 500 1k 2k 5k 10k fre qu ency (hz)
TDA7498 characterizations doc id 16107 rev 8 15/28 figure 10. fft performance (0 dbfs) figure 11. fft performance (-60 dbfs) fft (db) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) -1 8 0 +0 -170 -160 -150 -140 -1 3 0 -120 -110 -100 - 9 0 - 8 0 -70 -60 -50 -40 - 3 0 -20 -10 fft (db) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) -1 8 0 +0 -170 -160 -150 -140 -1 3 0 -120 -110 -100 - 9 0 - 8 0 -70 -60 -50 -40 - 3 0 -20 -10
characterizations TDA7498 16/28 doc id 16107 rev 8 3.2.2 for r l = 8 figure 12. output power (thd = 10%) vs. supply voltage figure 13. thd vs. output power 10 120 20 3 0 40 50 60 70 8 0 9 0 100 110 o u tp u t power (w) +10 + 3 6 +12 +14 +16 +1 8 +20 +22 +24 +26 +2 8 + 3 0+ 3 2+ 3 4 su pply volt a ge (v) 0.005 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 thd+n ( % ) 100m 200 200m 500m 1 2 5 10 20 50 100 o u tp u t power (w) f = 1 khz f = 100 hz
TDA7498 characterizations doc id 16107 rev 8 17/28 figure 14. thd vs. frequency (1 w) figure 15. thd vs. frequency (100 mw) figure 16. frequency response thd+n ( % ) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) 0.01 2 0.02 0.05 0.1 0.2 0.5 1 thd+n ( % ) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) 0.01 2 0.02 0.05 0.1 0.2 0.5 1 - 3 + 3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 ampl (db) 10 20k 20 50 100 200 500 1k 2k 5k 10k fre qu ency (hz)
characterizations TDA7498 18/28 doc id 16107 rev 8 figure 17. fft performance (0 db) figure 18. fft performance (-60 db)

fft (db) 20 20k 50 100 200 500 1k 2k 5k 10k fre qu ency (hz) -1 8 0 +0 -170 -160 -150 -140 -1 3 0 -120 -110 -100 - 9 0 - 8 0 -70 -60 -50 -40 - 3 0 -20 -10
TDA7498 applications information doc id 16107 rev 8 19/28 4 applications information 4.1 applications circuit figure 19. applications circuit for 6- or 8- speakers l+ r+ r- vcc gnd l+ l- r+ r- tda749 8 mute s tby 3 v 3 power s uppl y s ingle-ended * * * * * inp u t cla ss -d amplifier * * * * s ingle-ended inp u t lo a d = 6 ohm for for frequency s hift output input l- * lc filter component s lo a d l1,l2,l 3 ,l4 c20,c26 c1 8 ,c22,c24,c2 8 6 ohm 8 ohm 22 u h 22 u h 470 nf 6 8 0 nf 220 nf 220 nf c5 100nf r 3 3 9k l4 22 u h c1 1 u f c2 1 u f c11 1 u f c12 1 u f c 8 100nf c25 100nf c19 100nf c27 33 0pf r6 22r c40 220nf c41 220nf c21 33 0pf r5 22r c42 220nf c4 3 220nf c14 1nf 3 2 inpb 3 6 v ss 9 outnb 5 pgndb 7 pvccb 3 outpb 10 outna 12 pvcca 14 pgnda 16 outpa 33 innb 8 outnb 4 pgndb 21 mute 6 pvccb 2 outpb 29 s vr 11 outna 1 s ub_gnd 22 inpa 2 3 inna 27 s gnd 26 vdd s 2 8 diag 19 vddpw 1 8 pgnd 20 s tby 24 ro s c 3 1 gain1 3 5 s vcc 3 0 gain0 25 s ynclk 17 outpa 15 pgnda 3 4 vref 1 3 pvcca ic1 tda749 8 r1 100k r7 22r c6 100nf r4 120k r2 33 k r 8 6. 8 k c26 6 8 0nf c10 100nf c20 6 8 0nf j6 j5 2 1 3 s 1 2 1 3 s 2 c29 2.2 u f 2 gnd 1 out 3 in ic2 l49 3 1cz 3 3 1 2 j2 j 8 j7 + c2 3 2200 u f 50v l 3 22 u h l1 22 u h l2 22 u h j4 c 3 0 1 u f c 3 1 1 u f r14 100k r15 8 r c2 8 220nf r16 8 r c24 220nf r17 8 r c1 8 220nf r1 8 8 r c22 220nf 1 2 3 4 j 3 2 4 1 3 j1 r1 3 47k c1 3 1nf + c15 2.2 u f 16v + c7 2.2 u f 16v d1 1 8 v c9 100nf c4 1nf c 3 1nf c16 10 u f 10v c17 10 u f 10v r9 1 8 0k 1 2 3 q1 ktc 38 75( s ) diag vcc 3 v 3 3 v 3 f s f s vdd s vdd s
applications information TDA7498 20/28 doc id 16107 rev 8 4.2 mode selection the three operating modes of the TDA7498 are set by the two inputs, stby (pin 20) and mute (pin 21). standby mode: all circuits are turned off, very low current consumption. mute mode: inputs are connected to ground and the positive and negative pwm outputs are at 50% duty cycle. play mode: the amplifiers are active. the protection functions of t he TDA7498 are enabled by pullin g down the voltages of the stby and mute inputs shown in figure 20 . the input current of the corresponding pins must be limited to 200 a. figure 20. standby and mute circuits figure 21. turn on/off sequence for minimizing speaker ?pop? table 7. mode settings mode stby mute standby l (1) 1. drive levels defined in table 6: electrical s pecifications on page 8 x (don?t care) mute h (1) l play h h stby mute 0 v 3.3 v c7 2.2 f r2 30 k standby 0 v 3.3 v c15 2.2 f r4 30 k mute TDA7498 vcc stby mute input output i q standby mute play mute standby t t t t t t 0 0 0 0 0 0
TDA7498 applications information doc id 16107 rev 8 21/28 4.3 gain setting the gain of the TDA7498 is set by the two inputs, gain0 (pin 30) and gain1 (pin31). internally, the gain is set by changing the feedback resistors of the amplifier. 4.4 input resistance and capacitance the input impedance is set by an internal resistor ri = 60 k (typical). an input capacitor (ci) is required to couple the ac input signal. the equivalent circuit and frequency response of the input components are shown in figure 22 . for ci = 470 nf the high-pass filter cutoff frequency is below 20 hz: f c = 1 / (2 * * ri * ci) figure 22. input circuit and frequency response table 8. gain settings gain0 gain1 nominal gain, g v (db) ll25.6 lh31.6 hl 35.6 hh37.6 ri input ci rf input pin signal
applications information TDA7498 22/28 doc id 16107 rev 8 4.5 internal and external clocks the clock of the class-d amplifier can be generated internally or can be driven by an external source. if two or more class-d amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. this can be implemented by using one TDA7498 as master clock, while the other devices are in slave mode, that is, externally clocked. the clock interconnect is via pin synclk of each device. as explained below, synclk is an output in master mode and an input in slave mode. 4.5.1 master mode (internal clock) using the internal oscillator, th e output switching frequency, f sw , is controlled by the resistor, r osc , connected to pin rosc: f sw = 10 6 / ((r osc * 16 + 182) * 4) khz where r osc is in k . in master mode, pin synclk is used as a clock output pin whose frequency is: f synclk = 2 * f sw for master mode to operate correctly then resistor r osc must be less than 60 k as given below in ta b l e 9 . 4.5.2 slave mode (external clock) in order to accept an external clock input the pin rosc must be left open, that is, floating. this forces pin synclk to be internally configured as an input as given in ta bl e 9 . the output switching frequency of the slave devices is: f sw = f synclk / 2 figure 23. master and slave connection table 9. how to set up synclk mode rosc synclk master r osc < 60 k output slave floating (not connected) input synclk rosc rosc cosc rosc synclk 39 k 100 nf output input master slave TDA7498 TDA7498
TDA7498 applications information doc id 16107 rev 8 23/28 4.6 output low-pass filter to avoid emi problems, it may be necessary to use a low-pass filter before the speaker. the cutoff frequency should be larger than 22 khz and much lower than the output switching frequency. it is necessary to choose the l and c component values depending on the loud-speaker impedance. some typical values, which give a cutoff frequency of 27 khz, are shown in figure 24 and figure 25 below. figure 24. typical lc filter for a 8- speaker figure 25. typical lc filter for a 6- speaker
applications information TDA7498 24/28 doc id 16107 rev 8 4.7 protection functions the TDA7498 is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. overvoltage protection (ovp) if the supply voltage exceeds the value for v ovp given in table 6: electrical specifications on page 8 the overvoltage protection is activated which forces the outputs to the high-impedance state. when the supply voltage falls back to within the operating range the device restarts. undervoltage protection (uvp) if the supply voltage drops below the value for v uvp given in table 6: electrical specifications on page 8 the undervoltage protection is activated which forces the outputs to the high-impedance state. when the supply voltage recovers to within the operating range the device restarts. overcurrent protection (ocp) if the output current exceeds the value for i ocp given in table 6: electrical specifications on page 8 the overcurrent protection is activated which forces the outputs to the high-impedance state. periodically, the device attempts to restart. if the overcurrent condition is still present then the ocp remains active. the restart time, t oc , is determined by the r-c components connected to pin stby. thermal protection (otp) if the junction temperature, t j , reaches 145 c (nominally), the device goes to mute mode and the positive and negative pwm outputs are forced to 50% duty cycle. if the junction temperature reaches the value for t j given in table 6: electrical specifications on page 8 the device shuts down and the output is forced to the high-impedance state. when the device cools sufficiently the device restarts. 4.8 diagnostic output the output pin diag is an open drain transistor. when any protection is activated it switches to the high-impedance state. the pin can be connected to a power supply (< 39 v) by a pull-up resistor whose value is limited by the maximum sinking current (200 a) of the pin. figure 26. behavior of pin diag for various protection conditions TDA7498 protection logic r1 diag vdd vdd overcurrent protection restart restart ov, uv, ot protection
TDA7498 package mechanical data doc id 16107 rev 8 25/28 5 package mechanical data the TDA7498 comes in a 36-pin powersso package with exposed pad up. figure 27 shows the package outline and ta bl e 1 0 gives the dimensions. in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 10. powersso36 epu dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.45 0.085 - 0.096 a2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g- - 0.10 - - 0.004 h 10.10 - 10.50 0.398 - 0.413 h- - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 4.90 - 7.10 0.193 - 0.280
package mechanical data TDA7498 26/28 doc id 16107 rev 8 figure 27. powersso36 epu outline drawing h x 45
TDA7498 revision history doc id 16107 rev 8 27/28 6 revision history table 11. document revision history date revision changes 11-aug-2009 1 initial release. 27-aug-2009 2 updated supply voltage range on page 1 updated package exposed pad dimension y (min) in table 10 on page 25 . 23-oct-2009 3 updated first feature on page 1 updated order code name in table 1 on page 1 updated table 5: electrical specifications on page 8 updated section 3.2: characterization curves on page 13 removed tables for standby, mute and gain after figure 19 on page 19 . 30-jun-2010 4 removed datasheet preliminary st atus, updated features list and updated device summary table on page 1 added table 5: recommended operating conditions on page 8 with updated minimum supply voltage. 27-jan-2011 5 updated applications circuit in figure 19 on page 19 . 11-feb-2011 6 updated test circuit for characterizations in figure 3 on page 11 . 29-mar-2011 7 updated i ocp in table 6: electrical specifications . 12-sep-2011 8 updated outna in table 2: pin description list
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